Key factors in Die level reliability estimation
1. Field Distortion
Cause: Polar molecules (i.e. water and ionic contaminants) on passivation surface and die’s edge
Effect: Increased local leakage current and thermal runaway due to distorted electric field when high voltage is applied.
The failure rate is accelerated by HTRB & HTB test conditions. The best case is the device with the lowest voltage rating type
in the family. The worst case device types are those that produce the highest field strengths.
2. Oxide Defects
Cause: Defects in the gate oxide
Effect: Lead to failures in the form of a gate-to-source short circuit
They can be activated by high-temperature gate-stress/bias (HTGS or HTGB) testing. The worst case device is subjected to
the greatest field strength at the highest temperature.
Key factors in Package level reliability estimation
1. Die Attach Fatigue
Cause: Different in thermal expansion coefficients of silicon and the header material causing differential movement.
Effect: Cracking or separation of the die or voiding of the die attach, resulting in degraded-on-resistance and/or thermal
fatigue.
The susceptibility of a given die attach to thermal fatigue is normally ascertained with power cycling or unbiased
temperature cycling. The best case device has the weakest internal physical stress, thus the smallest die size. The worst
case device is the largest die size in the family.
2. Metal Corrosion
Cause: Ingression of water into the chip surface, forming external surface leakage paths. Further, internal
package stresses can promote moisture ingression allowing moisture paths to occur.
Effect: Excessive drain current and eventually parametric failure.
An open circuit can result from the cathodic corrosion of the source pad when a reverse bias voltage is applied (with Vgs=0).
The best case device has the smallest die with the lowest voltage rating. The worst case device has the largest die with the
highest voltage rating.
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