• Solder standoff trials
• Screen aperture design
• Placement force
• Solder vendors
• Substrate bend strength measurements
• Package parasitics
• Shock/drop testing
• Vibration testing

• Temperature/power cycling on IMS
• Temperature/power cycling on ceramic
• Temperature/power cycling on Pb-free solder
• High frequency parasitic evaluation
• HTRB, HTGB, THB
• Moisture absorption

• The matrix qualification philosophy uses the homogeneous nature of the MOS switch, i.e. hundreds or thousands of identical structures placed in paralleled on the same die.
• The chips’ lengths and widths will vary depending on the device, but in any case all devices of the same family should age the same way.
• The matrix qualification philosophy allows us to exploit the homogeneity of the family.
• For a given environmental test, there will be one specific part type from the family which has been found or is expected to be found to have the highest failure rate, that is the worst case part. For example:
  • Large die -> more susceptible to thermo-mechanical stress.
  • Larger gate surface area -> higher TDDB failure probability.
  • Large field termination structure area -> more likely affected by micro contaminants.
• On the other hand, there is also one part type which would be expected to see the least amount of stress, that is the best case part. For example, the smallest die in the family with the lowest VDS rating.
• Two aspects of reliability must be assessed: package level reliability and die level reliability.

“The worst and best case parts bracket the rest of the part types within the family, for a given test”. This statement holds only if the family members have been chosen well.

Thus there are three key factors in the matrix qualification process:

• Select the families and family members correctly
• Identify critical devices attributes
• Choose appropriate reliability tests for best and worst case part types

Die Level

1. Field Distortion
Cause: Polar molecules (i.e. water and ionic contaminants) on passivation surface and die’s edge
Effect: Increased local leakage current and thermal runaway due to distorted electric field when high voltage is applied.
The failure rate is accelerated by HTRB & HTB test conditions, where the field strength depends on the selected bias.
The best case is the device with the lowest voltage rating type in the family.
The worst case device types are those that produce the highest field strengths.

2. Oxide Defects
Cause: Defects in the gate oxide
Effect: Lead to failures in the form of a gate-to-source short circuit
They can be activated by high-temperature gate-stress/bias (HTGS or HTGB) testing.
Since there are four variables involved (bias applied, junction temperature, stress duration
and gate oxide thickness) the worst case device is subjected to the greatest field strength at the highest temperature.

Package Level

1. Die Attach Fatigue
Cause: Different in thermal expansion coefficients of silicon and the header material causing differential movement.
Effect: Cracking or separation of the die or voiding of the die attach, resulting in degraded on-resistance and/or thermal fatigue.
The susceptibility of a given die attach to thermal fatigue is normally ascertained with power cycling or unbiased temperature cycling).
The best case device has the weakest internal physical stress, thus the smallest die size.
The worst case device is the largest die size in the family.

2. Metal Corrosion
Cause: Ingression of water into the chip surface, forming external surface leakage paths. Further, internal package stresses can promote moisture ingression by corrupting the integrity of the mold compound and allowing moisture paths occur.
Effect: Excessive drain current and eventually parametric failure.
The application of reverse bias under blocking conditions (VG = VS) can result in cathodic corrosion of the source pad, leading eventually to an open circuit.
The best case device has the smallest die with the lowest voltage rating.
The worst case device has the largest die with the highest voltage rating.