DirectFET®; MOSFET: Small Can Substrate Layout
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ST Small Can Outline, Substrate Layout |
ST Stencil Design
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ST-outline device outline
The relative pad positions are controlled to an accuracy of ±0.065mm. |
ST-outline substrate layout
Aperture Tolerance = ±0.025mm
Positional Tolerance = ±0.075mm |
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NOTE: Gate and source pads on the substrate are oversized by 0.025mm (0.001”) on each side.
Drain pads are thickened by 0.500mm (0.020”). |
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SH Small Can Outline, Substrate Layout |
| SH Stencil Design
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SH-outline device outline
The relative pad positions are controlled to an accuracy of ±0.065mm. |
SH-outline substrate layout
Aperture Tolerance = ±0.025mm
Positional Tolerance = ±0.075mm |
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NOTE: Gate and source pads on the substrate are oversized by 0.025mm (0.001”) on each side.
Drain pads are thickened by 0.500mm (0.020”). |
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SJ Small Can Outline, Substrate Layout |
| SJ Stencil Design
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SJ-outline device outline
The relative pad positions are controlled to an accuracy of ±0.065mm. |
SJ-outline substrate layout
Aperture Tolerance = ±0.025mm
Positional Tolerance = ±0.075mm |
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NOTE: Gate and source pads on the substrate are oversized by 0.025mm (0.001”) on each side.
Drain pads are thickened by 0.500mm (0.020”).
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IR’s proprietary DirectFET®; technology is covered by US Patent 6,624,522 and
other US and foreign pending patent applications.
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