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INTERNATIONAL RECTIFIER INTRODUCES HEXFET® POWER MOSFETS IN FLIPFET® PACKAGES ENABLING WORLD'S HIGHEST POWER DENSITY
New Power MOSFET Packaging Achieves 100% Silicon-to-Footprint Ratio
EL SEGUNDO, CA. June 2000 - International Rectifier (IR®) has introduced new HEXFET® power MOSFETs in proprietary packages in which all of the terminals are on a single side of the die. The new FlipFET® power MOSFETs will enable a new generation of super-compact power architectures with better power density for advanced portable applications.
The first two products being introduced using this technology are the 20V P-channel IRF6100 (single) and IRF6150 (bi-directional dual). Remarkably, the IRF6100 measures just 1.52mm square, and the IRF6150 is only 3.05mm square.
These revolutionary new FlipFET® devices embody true chip scale packaging (CSP) technology, giving rise to a new generation of super-compact power architectures with increased power density. This packaging technology is ideal for advanced portable applications, where space is a premium.
"The FlipFET® devices have a 100% silicon-to-footprint ratio. Since the die is the package, stray inductance and other losses associated with device packaging are minimized or eliminated. As a bonus, the MOSFET footprints are reduced by more than 70% to one-third those of popular TSOP-6 and SO-8 packages while providing the same or better performance," says Jorge Llorens, technical marketing manager at IR.
Reducing the footprint is just one potential gain. FlipFET® packaging improves on-resistance and thermal performance. For example, a 20V P-channel FlipFET® device with the same footprint as the industry standard TSOP-6 would have an RDS(on) of 14 milliohms max. This would be 88% lower than an industry-standard Si3443DV.
Thermal performance of FlipFET® devices will be at least equivalent to the industry standard outline but in approximately one-third of the area.
Like all surface-mount devices, overall thermal performance is limited by board design and area of bump contact to the board. Results can vary from 10°C/W junction-to-board to 230°C/W junction-to-ambient on minimum footprint.
The FlipFET® devices feature 0.25mm diameter eutectic solder (63Sn37Pb) bumps with 0.8mm pitch for standard SMT assembly, and are designed to require no under-fill. The solder bump dimensions are similar to those found on ball grid array (BGA) and chip scale packaged (CSP) devices. Bumps self-align to board pads, and placement errors of up to 0.125mm can be accommodated during assembly.
Many cell phone Li-Ion smart battery packs presently use dual SO-8 MOSFETs. By using FlipFET® device technology, it is possible to shrink circuit size considerably. Hence, for the same overall battery pack size, fuel cell volume could be increased by nearly 20%. This would equate to an estimated 30 minutes of talk time on a standard three-hour Li-Ion-type battery.
With the advent of 3G Internet-enabled multimedia cell phones, added functionality will mean a higher power requirement. FlipFET® technology will not be a design alternative, it will be the only solution to meet or exceed talk time expectations in the same outline.
In automotive applications where multi-chip modules are commonplace, the FlipFET® package may replace wire-bonded devices and drastically alleviate space constraints in engine compartment applications.
The new IRF6100 and IRF6150 FlipFET® power MOSFETs are available fully tested, packaged bumps-down on tape and reel.
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