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The XPhase architecture is crafted for multiphase interleaved buck DC-DC
converters requiring 1 to “X” phases with flexibility to facilitate rapid design
trade-offs. It comprises a control IC and a scalable array of phase converters, each
using a single phase IC as shown in Figure 1. The control IC IR3081 communicates
with phase ICs IR3086 through a novel 5-wire analog bus that consists of bias
voltage, phase timing, average current, error amplifier output and VID voltage. By
eliminating the need for point-to-point wiring between the controller and the phase ICs, the 5-wire bus shortens the interconnects to cut parasitic inductance and noise. The control device contains all the one-per converter circuitry, which includes voltage identification (VID), PWM ramp oscillator, error amplifier, bias voltage, fault detection, and other necessary functions
to meet the load line, as well as transient response, requirements of the present and future microprocessors. Each phase IC comprises all one-per phase circuitry that includes gate drivers, PWM comparator and latch, overvoltage protection, and current sensing and sharing.
Figure 1. XPhase Control Architecture showing Control IC, 5-wire bus and Phase ICs
Because accurate current sharing is critical to multiphase designs, XPhase architecture implements a loss-less average inductor current sensing technique. By comparison to other
sensing methods, average inductor sensing offers better accuracy at lower cost, and presents no errors due to sampling, ripple and duty cycle variations. In addition, unlike other architectures, it also supports single cycle transient response. Current sense resistors cost more, take up space, dissipate heat, and reduce efficiency. Although, current sense resistors can achieve +/-1% initial accuracy, they contribute parasitic inductance that limits high frequency switching.
To ensure accurate current sharing amongst the distributed phase
converters, an average current share bus is utilized, which connects
to each phase IC. The output of the current sense amplifier is compared
with the average current on the share bus. If the current in a phase
is smaller than the average current, the share adjust amplifier
of the phase will activate a current source that reduces the slope
of its PWM ramp thereby increasing its duty cycle and output current.
In this case, the bandwidth of the current share loop is programmed
to be slower than that of the voltage loop, so that the two loops
do not interact.
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