As the size of the DC-DC converters shrink, thermal management becomes increasingly difficult. There is less and less PCB area to dissipate the heat generated by the various components. Optimized silicon technology has improved MOSFET characteristics to the point where packaging has become the next frontier to higher performance MOSFETs. For example, industry benchmark MOSFET, IRF7832, has an R_DS(ON) of 3.7mOhms typ. @ 4.5V_GS, 50% which is due to the resistance of the SO-8 package it is housed in.

The SO-8 package has poor thermal characteristics, is not easy to heatsink and can only effectively be cooled on one side, leading to most of the heat being dissipated through the PCB. None of the new SO-8 derivatives such as Siliconix PowerPak™ (leadless SO-8), Hitachi FL pak and Fairchild Bottomless SO-8™ recently introduced in the market has effectively addressed the need to remove the heat away from the PCB itself. While they have demonstrated great improvement in the junction-to-PCB thermal resistance, they remain single-side cooled solutions because the top-side thermal resistance was not improved.

Patented DirectFET technology is the first surface mount package designed from the ground up for power semiconductors. It has a uniquely simple construction that provides breakthroughs in die free package resistance and heat dissipation capabilities, dramatically increasing efficiency and current carrying capacity of the device in a given footprint.

DirectFET Package construction

The Silicon die is contained in a copper housing. The bottom of the package consists of a die specifically designed with source and gate contact pads that can be soldered directly to the PCB. The copper 'can' forms the drain connection from the other side of the die to the board. A proprietary passivation system on the silicon die isolates the gate and the source pads to prevent shorting when the device is mounted on the PCB. The passivation protects the termination and gate structures from moisture and other contamination normally encountered during PCB assembly process. This design eliminates the lead-frame and wire bonds, reducing die-free package resistance (DFPR) to be less then 150µW in an SO-8 footprint compared to 1.5mOhms for the standard SO-8 package.