Post reflow tilt (across)
Tilt on devices post reflow can only occur for a number of reasons. Tilt across the device, as shown in the photo at the right, normally results from too much solder (particularly under drain contacts) stencil reductions and or extending the drain pad sizes should eliminate this problem (see post reflow tilting layouts below).

Up to 3° of tilt can be tolerated although up to 1° would be more normal. Fundamentally this problem should be cured by stencil layout, although it can often be improved as a result of better wetting. Wetting will change with solder and reflow profile.

NOTE: if you are using top side Heatsinking, you may have problems mounting heatsinks to tilted devices!

Tilt on devices post reflow can only occur for a number of reasons. Tilt along the length of the device above 1° should not occur. Tilt along the length is generally caused by uneven heating. This may be due to one end of the device being mounted on a very large are of copper or on the same pad as a very large component (fig 2).

Some times this problem is described in smaller components as “tombstoning” and is when the solder at one end of the device goes liquid before the other, the surface tension becomes uneven and the devices tries to lift. In the case of DirectFET the device does not hinge up completely but is enough to cause tilt in some instances.

Post reflow tilt (along device length)
Ideally tilt along this axis, if due to device location, should be remedied by limiting the thermal mismatch. The device can be moved or the copper areas balanced.

This is often not possible and the result is using techniques to limit the effect. The most effective is to increase the thermal energy available to make the solder joint. If a line is drawn across the reflow profile at the point that the solder goes liquid (183°C Sn63 Pb37) the area of the profile that is above this is the energy available for soldering. Time or temperature in this region needs to be increased.

It is important that the area of the board that the component is mounted on is the area that is measured. It is also important to note that a populated board is likely to give a lower temperature than an unpopulated one (bare board).

See following profile graph.

There are some tricks that can be used to overcome time over 183°C if peak temperature or general time over 183°C cannot be altered.

If the area of board that the DirectFET MOSFET is on lags in temperature, extending soak time can increase time over peak. This allows all of the areas of the board more time to even out at 150-175°C and means that they are also closer over 183°C .

There are physical changes to substrate and stencil outlines that can also help. newer outlines include extended drain pads 0.9mm. This helps by depositing more solder paste outside of the footprint area, which can help to equalise the effects of the surface tension (see substrate and stencil outlines).

General comments:
Board surface finish will have an effect on how much energy is required to solder the joint, changing from nickel gold to HASL (soldered finish) reduces energy required.

Nitrogen reflow atmosphere makes “tombstoning” worse!

• This is really undesireable
• The effect is rare
• Tombstoning is caused by differential surface tensions across the device, uneven heating rates are a likely cause