Preconditioning: consisting of temperature and humidity soak followed by reflow (eg. 168Hrs @ 85°C/85% RH followed by 3 x reflow @ peak temp of 260°C).

• The level of preconditioning given to components ultimately decides the MSL (moisture sensitivity level) of the package.
• MSL level 1 represents the most extreme levels of preconditioning, and hence the best resistance to moisture and other atmospheric conditions. If a package cannot attain MSL level 1, then it is downgraded to MSL level 2 or less.
• Packages assigned these lower MSL levels are required to be dry-packed, which is highly undesirable from a manufacturing point of view.
• The increased temperatures of lead-free reflow profiles could lead to reduction in the MSL level of power components.
• The other qualification tests, like HTRB, HTGB, H³TRB are carried out after the components have gone through preconditioning.

	Floor Life		Soak Requirements
			Standard		Accelerated
Level	Time	Cond. °C/%RH	Time (hrs)	Cond. °C/%RH	Time (hrs)	Cond. °C/%RH
1	unlimited	<=30/85%	168 +5/-0	85/85	n/a	n/a
2	1 year	<=30/60%	168 +5/-0	85/60	n/a	n/a
2a	4 weeks	<=30/60%	696 +5/-0 (2)	30/60	120 +1/-0	60/60
3	168 hours	<=30/60%	192 +5/-0 (2)	30/60	40 +1/-0	60/60
4	72 hours	<=30/60%	96 +2/-0 (2)	30/60	20 +0.5/-0	60/60
5	48 hours	<=30/60%	72 +2/-0 (2)	30/60	15 +0.5/-0	60/60
5a	24 hours	<=30/60%	48 +2/-0 (2)	30/60	10 +0.5/-0	60/60
6	TOL (1)	<=30/60%	TOL	30/60	n/a	60/60

1) TOL means 'Time on Label', or the time indicated on the label of the packing.
2) The Standard soak time = 24H + floor life, where the 24H term is the default value of the semiconductor manufacturer's exposure time (MET) between bake and bag while the “Floor Life “ is maximum time allowed out of the bag at the end user or distributor's facility (i.e MSL 3 package will require 168 hours of floor life plus 24 hours between bake and bag at the semiconductor manufacturer.

Part Number	Abbrev.	Test Description	Test Conditions	Instructions/ Duration	N Lots/ Device per lot	Notes
As Above	.	Pre and Post Electrical Test	Electrical characterization @25°C	All Tests	.	.
	EV	External Visual	All Test Samples	.	.	.
	PV	Parametric Verification	Characterization @ Room temp & Tj max.	Not required	-	.
	HTRB	High Temperature Reverse Bias	150°C, 80% VGS Rated Voltage (on boards)	500 Hours	3/80	.
	HTGB	High Temperature Gate Bias	150°C, 80% VDS Rated Voltage (on boards)	500 Hours	3/80	.
	T/C1	Temperature Cycling	125°C to -40°C (on boards)	500 Cycles	3/80	.
	H3TRB	High Humidity, High Temperature Reverse Bias	80% VDS Rated Voltage 85°C/85% RH (on boards)	500 Hours	3/80	.
	TR	Thermal Resistance	ZθJC RθJC	Monitor T/C Post T/C and IOL	3/80	A, B

Notes:
A. Zθ Testing will be monitored at pre-test, interim and end point electrical tests.
B. Rθ Samples shall be selected from worst-case Zθ results of T/C post 1k cycles for compliance with datasheet requirements

Part Number	Abbrev.	Test Description	Test Conditions	Instructions/ Duration	N Lots/ Device per lot	Notes
As Above	.	Pre and Post Electrical Test	Electrical characterization @25°C	All Tests	.	.
	EV	External Visual	All Test Samples	.	.	.
	PV	Parametric Verification	Characterization @ Room temp & Tj max.	Per data sheet specification	3/80	.
	HTRB	High Temperature Reverse Bias	150°C, 80% VDS Rated Voltage (on boards)	1000 Hours	3/80	.
	HTGB	High Temperature Gate Bias	150°C, 80% VGS Rated Voltage (on boards)	1000 Hours	3/80	.
	T/C1	Temperature Cycling	125°C to -40°C (on boards)	1000 Cycles	3/80	.
	T/C2	Temperature Cycling	150°C to -55°C (on boards)	1000 Cycles	3/80	C
	H3TRB	High Humidity, High Temperature Reverse Bias	80% VDS Rated Voltage 85°C/85% RH (on boards)	1000 Hours	3/80	.
	IOL	Intermittent Operational Life	Ton/off ≥ 2 minutes Tj max=105°C (on boards)	15,000 Cycles	3/80	.
	TR	Thermal Resistance	ZθJC RθJC	Monitor T/C	3/80	A, B
	MSL	Moisture Sensitivity	J-STD-020	2 lots of each die size	2	.

Notes:
A. Zθ Testing will be monitored at pre-test, interim and end point electrical tests.
B. Rθ Samples shall be selected from worst-case Zθ results of T/C and IOL post 1k cycles and 5k cycles respectively for compliance with datasheet requirements
C. A second temperature cycling test will be carried out to confirm datasheet specified storage temperature. Any failure that is found to be attributed to the DUT card or mounting process will be classified as non-valid.

• V_S = V_G = 0V
• V_D = 80% Maximum rated BV_DSS
• Hours: Depending on qualification
• 150°C
• Accelerates blocking voltage degradation

Failure Modes

• Degradation of BV_DSS. Most common failure in HTRB. Primarily caused by the presence of foreign materials and polar/ionic contaminants. These migrate under temperature and bias and perturb the electric field at the termination.
• Degradation of V_th. This failure mode is rare.

Sensitive parameters: BV_DSS, I_DSS, I_GSS, V_th.

• V_S = V_D = 0V
• V_G = 80% Rated V_GS
• Hours: Depending on qualification
• 150°C
• Accelerates Time Dependent Dielectric Breakdown (TDDB) of the gate structure

Failure Modes

• Gate oxide rupture: Most common failure in HTGB. Primarily caused by the degradation with time of defects in the thermally grown oxide. Manifests as resistive short from g-s or g-d.
• Degradation of V_th. Caused by the presence of mobile ionic contaminants in the gate oxide, which migrate to the surface under bias and temperature. This can cause a shift in the threshold voltage. This failure mode is rare.

Sensitive parameters: I_GSS, V_th

• Temperature
  • T_{ON board}= 95°C (T_J-max <105°C)
  • T_max= 30°C + DT, DT = 70°C or 100°C
• Bias
  • V_S = 0, V_G = 10.5V_(on)/0V_(off)
  • I_DS = 250mA
  • 15k Cycles
  • Simulates thermal and current pulse stresses that the device would see in real applications.

Purpose: The purpose of power cycling is to simulate the thermal and current pulsing stresses which devices will encounter in actual circuit applications when either the equipment is turned on and off or the power is applied to the device in short bursts interspersed with quiescent, low power periods. The simulation is achieved by the on/off application of power to each device while they are in the active linear region.

Failure Modes

• Degradation of metal-metal or metal-silicon interfaces. Primarily caused by thermo-mechanical stresses from heating and cooling. Wire bond degradation causes an increase in R_DS(on), while die attach degradation gives rise to an increase in R_th-jc.
• Die cracking. Can give rise to gate shorts or leakage

• Temperature
  • T_min= -40°C
  • T_max= 125°C
  • No applied bias
  • Cycles: Depending on qualification

Purpose: The purpose of temperature cycling is to simulate thermal stresses which devices will encounter in the actual circuit applications (as with power cycling) in combination with potentially extreme operating ambient temperatures. Some equipment is destined to be used in extreme environments, and subject to daily temperature cycles.

Simulates thermal pulse stresses that the device would see in real applications in combination with extreme ambient temperatures

Failure Modes (same as power cycling)

• Degradation of metal-metal (wire bonds) or metal-silicon (die attach) interfaces.
• Die cracking.

• Temperature= 85°C
• Relative Humidity = 85%
• Bias
  • V_S= V_G= 0V
  • V_D= 80% Maximum rated BV_DSS up to maximum of 100V
• Hours: Depending on qualification
• Submits non-hermetic packages to temperature and humidity stress.

Purpose: The purpose of temperature-humidity-bias testing is to subject non-hermetic encapsulated devices to temperature and humidity extremes with bias on the drain. This test is a method of examining the ability of a non-hermetic package to withstand the deleterious effects of a humid environment. The devices are placed in a temperature and humidity chamber at ambient pressure and are biased in a cut-off mode.

Failure Modes

• Degradation of BV_DSS. Ingression of water molecules can cause perturbation of the electric field at the device termination.
• Cathodic corrosion of aluminum bond pads. Results from current flow in water molecules present.

• When the gate-source voltage is high enough to arc across the gate dielectric (ESD) , a microscopic hole is burned in the gate oxide.
• More than likely, this will not cause immediate failure, but as mentioned already can give rise to long term reliability issues.
  • Degradation in blocking capability BV_DSS.
  • Degradation in gate oxide integrity I_GSS.