(1) Place output Capacitors very close to fast load chips (CPU, DSP, etc). Smaller capacitors had better to be placed closer to those fast load chips.  

(2) Use multiple layers to provide high current to high performance fast load chips. If possible, use same number of Vout layers and same number of Ground layers underneath the high performance fast load chips.  

(3) Use multiple VIAs (through-holes) to connect the internal layers to the top/bottom layer output Capacitors and fast load chips. To reduce internal layer copper conduction interrupting (blocking), place two VIAs or four VIAs in groups and overlap their O.D. pads to give more space for internal layers. The VIAs had better to be covered with protective paint to avoid solder paste from flowing through those VIAs during high volume SMT machine soldering.  

(4) Place output Inductors very close to the output Capacitors (in case of multi-phase applications, if possible, please use same distance copper resistance between each output Inductors to the fast load chips.  

(5) Output Inductor switching node Schottky Diode had better be placed close to output Inductor too and use very thick trace or polygon. Please use as many internal copper layers to help reduce copper conduction loss as possible. If possible please use as many VIAs to connect the terminals of Schottky Diode to internal layer coppers to reduce copper trace conduction loss.

(6) The Trace between low-side MOSFETs and output Inductor has to be short and wide. Please use as many internal copper layers to help reduce copper conduction loss as possible. If possible please use as many VIAs to connect the terminals of Source pads and Drain pads to internal layer coppers to reduce copper trace conduction loss.

(7) The Trace between high side MOSFET and output Inductor has to be short and wide. If possible please use around 1/3 number of VIAs used in low side MOSFET to connect the terminals of Source pads and Drain pads to internal layer coppers to reduce copper trace conduction loss.  

(8) If possible, please use multiple layers of polygon to connect the above switching node (between high-side MOSFET, low-side MOSFET, Schottky Diode, and output Inductor). Please do not route high-speed small signal swing signal traces too close to the switching node polygon. Please keep at least 15 mils distance between the switching-node from those fast small signal traces. Please don’t route small signal traces above or underneath the switching node polygon either.  

(9) Place the input Capacitors close to the high side MOSFETs. In case of multi-phase design, divide equally the Input capacitors to all phases’ high side MOSFETs.

(10) If possible, add one small 2nF 0603 Capacitor close to the high side MOSFET "Drain Pin". The rings in Input Capacitor and switching node might be able to be reduced.  

(11) Put more VIAs (through-holes) close to the low side MOSFET "Source Pin" pad. For DirectFET, you can put 20 VIAs (12mil ID, 24 mils OD) on the Source pads like drawing-1.

(12) In case you want to dual layout the DirectFET (low side DirectFET has bigger Source pads and is more difficult) with SO-8, the drawing 02 below is one good example to follow.