• Processors have been consistently tracking and possibly outpacing Moore’s law
• This has enabled significant advances in processor capability and functionality, but at what cost?

• Power losses are increasing and board space is being reduced
• Significant issues are arising with Desktop, Transportable, Mobile and 1U Servers
• Top sided cooling will soon become “standard” in VRM/VRD’s

• First order cooling limitations are based on the FET package and associated thermal resistances – this is predominantly an electrical engineering function and the mechanical engineer has to make it work
• Power densities and delta T’s are high - this is the first place to solve thermal issues!
• Paying a more for a better package can save significant time and money in the back end of the design
• Increases the power dissipated out of the package by removing the heat very efficiently through the top of the package.

SO-8

No topside cooling/sinking

• Sync buck running @ 300kHz
• Minimal heat spreading into board
• @ 18A device T_j=125°C

DirectFET®; Technology

No topside cooling/sinking

• Sync buck running @ 300kHz
• Minimal heat spreading into board
• @ 18A device T_j=75°C

Options

• No Heat Sinks
• Top Side Sinking
• Bottom Side Sinking
• Dual Sided Sinking

• Depending on what package you use, selecting top or bottom side sinking may or may not make a large difference (PowerPak, S0-8)
• Selecting top sided sinking makes a significant difference with DirectFET due to its extremely low j-c thermal resistance

• With top side cooling DirectFET is significantly better than PowerPak and SO-8
• To make the PowerPak and the SO-8 perform similar to the DirectFET would require additional costs for a better TIM and a larger sink – maybe even a better fan

• Z-thermal conductivity tests were performed on a 1” diameter PCB specimen (see photos in following slide)
• Measured thermal conductivity = 1.5 W/mK
  • PCB thickness = 0.080”
  • 10 Layers
  • 2 oz. copper