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DirectFET®; MOSFET Board Layout

Pads and Outlines

Die Recess
  • Forces standoff beneath gate and source pads which improves thermal fatigue resistance
  • Reduces incidence of solder balling
Surface Finish

DirectFET MOSFET Pads


Pad layout – Extended Drain Rail
  • Primarily designed to provide more fillet area to allow for pin-testing
  • Also helps to reduce tilt and device sensitivity to volume of solder on the drain pad
  • Reduces the centring ability of the device very slightly but not to a problematic level
  • In the old and extended versions the drain rails are split into two for both the copper on the board and the solder that is printed

DirectFET Package Outlines
The new method of outline identification breaks all of the low voltage devices into up to 3 die sizes* within each can.

* Each die size has it’s own specific pad layout. Refer to datasheets for exact dimensions. Refer to the following URL for further details: /technical-info/appnotes/an-1035.pdf
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IR’s proprietary DirectFET®; technology is covered by US Patent 6,624,522 and other US and foreign pending patent applications.

 
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Pads and Outlines
     Small Can Outline
     Medium Can Outline
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     Layout Examples
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