Glossary of Acronyms, Terms and Abbreviations
for International Rectifier Die Products

Term Definition
AC TestGeneral term used to describe tests that measure dynamic or switching parameters
AOIAutomated Optical Inspection
ASICApplication Specific Integrated Circuit. Semiconductor circuit specifically designed to suit a customer's particular requirement
Bare DieUnpackaged die, e.g integrated circuits, diodes and transistors
BondingThe process of connecting wires from the package leads to the chip or bonding pads
Bond PadsAn area on the periphery of a silicon die for making connection to one of the package pins
Bumped DieUnpackaged integrated circuit that has interconnect material formed in contact with the I/O to allow flip-chip attachment
ChipAlso called a die. Popular term describing a section of a wafer that contains a discrete component
Class BA screening process for circuits that are intended for use in ground-based military electronic systems
Class SA screening process for circuits that are intended for use in satellite systems for military space applications
COB(Chip on Board) A bare die that is attached to a rigid substrate face up and electrically interconnected to the substrate using wire bond technology
COF(Chip on Flex) A bare die that is attached to a flexible laminate substrate active side up and electrically interconnected to the substrate using wire bond technology
COGChip on Glass
CSPChip Scale Package
CTECoefficient of Thermal Expansion
C4Controlled-Collapsed Chip Connection
DCADirect Chip Attachment
DCTest General term used to describe tests that measure static parameters
DSCCDefence Supply Center, Columbus. The agency responsible for procurement of electronic supplies for the U.S. military
DPCDie Product Consortia
EEElement Evaluation
EMIElectromagnetic Interference
ESDElectrostatic Discharge
Eutectic Solder63% Tin, 37% Lead
FAFailure Analysis
Fab / FabricationIn semiconductor manufacturing, fabrication usually refers to the front-end process of making devices and integrated circuits in semiconductor wafer
FCPFew Chip Package
Film FrameSawn wafer on sticky tape supported by a metal frame
Flip ChipA method for electrically interconnecting unpackaged die active side down with a conductive bump to the substrate
Gel PackagePlastic trays used to shop unpackaged die. The die is held in place by surface tension of a membrane. A vacuum chuck is required to reduce surface tension and remove die
HDIHigh Density Interconnects
ICIntegrated Circuit
JEDECJoint Electronic Device Engineering Council
KGDKnown Good Die
LATLot Acceptance Test (also known as an element evaluation)
LTCCLow-Temperature Co-fired Ceramic
MCMMulti-Chip Module
MCPMulti-Chip Package
MIL-PRF-38534Specifications that establish general quality and reliability assurance requirements for hybrids.
MIL-PRF-38535Specifications that establish general quality and reliability assurance requirements for microcircuits.
MIL-STD-883Test methods and procedures for microelectronic devices for use in military and aerospace systems.
mvMicrovis technology creates a PC board via of <= 150mm (typically by non-mechanical means) and uses built-up multi-layer processes.
mBGAMicrog Ball Grid Array package
mSMDMicro Surface Mount Device
PWBPrinted Wiring Board
RFRadio Frequency
SCDSource Control Drawing
SEMScanning Electron Micrograph - high resolution photography that uses electrons rather than light waves to define an image
SiPSystem in a Package
S LevelWafer fabrication process and quality requirements as defined in MIL-PRF-38535
SMDStandard Microcircuit Drawing
SOCSystem on a Chip
SPCStatistical Process Control
TABTape Automated Bonding
Tape on ReelA high volume automated shipping method for automated assemble processing available on 7" or 13" reels.
TgGlass transition temperature
Total Dose Radiation (RHA)The total accumulated amount of ionizing radiation at a specified exposure rate that can be experienced by a microcircuit before its performance degradates below set limits. Typically measured per MIL-STD- 883, Method 1019
UBMUnder Bump Metallurgy
Waffle PacksPlastic trays with individualized pockets designed for a specific die size.
Wire BondDie assembly method in which die is bonded upright to substrate and electrical connections are made with gold or aluminium wire between the bond pads and traces on the substrate.
WLAWafer Lot Acceptance - certification that a wafer has passed a series of physical measurements including step coverage, SEM, surrent density and other measurement of critical dimensions.
WL-CSP Wafer-Level Chip Scale Package
WLPWafer-Level Packaging